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The Propeller does not use interrupts as most other microcontrollers do; all external signalling events must be detected by polling or by waiting for an incoming line to go high or low. With the Propeller's multi-Cog architecture this is not as much of a problem as it would be for a single core processor; with one or more Cogs dedicated to 'interrupt handling', idling until the appropriate signal conditions are met, other Cogs can continue processing unaffected.
Multiple interrupts where response latency is not critical can be handled by a single Cog polling each 'interrupt line' in a cyclic manner and responding as appropriate. Where low latency is required a single Cog can wait for the interrupt to occur and respond within just a few clock cycles. Such a Cog can only handle a single interrupt, but with multiple Cogs that again is not so much of a problem.
A Propeller Chip program can consist of a main program using a single Cog with the other Cogs dedicated as low-latency interrupt handlers. For the Propeller Chip this allows up to seven low-latency interrupts. Because each Cog is running independently to the others all multiple interrupts will be responded to in parallel - something which no single-core microcontroller can achieve except when interrupts are handled by chip hardware.
The on-chip counter hardware each Cog has can be used for short signal pulse detection. These can be used by a Cog which is polling to detect a signalling event and then respond to it at its leisure.
A Cog which is polling multiple interrupts can implement its own prioritorisation scheme for interrupt handling. As interrupts are being handled by polling it is also possible to have interrupt events dependent on the state of multiple signal lines rather than just a single signal. The polarity of all signal lines monitored can of course be specified under programmer control and any of the available I/O lines can be used to trigger interrupt events. Prioritorisation and so on can all be changed dynamically at run-time if necessary.
A mix of Cogs can be allocated to handle low-latency interrupts and polled interrupts giving flexible options to implement what would be called an interrupt architecture on other microcontrollers. What type of interrupt architecture is required or implemented is entirely in the hands of the designer and programmer not forced by the chip designer.
Users of more traditional microcontrollers are often taken aback when they discover that the Propeller does not support interrupts. For all intents and purposes it does, but not in the way that a single core processor has its program flow interrupted while an interrupt event is handled.
As with many things Propeller related ( and it is the same with any multi-core processor ) it is really just a case of doing things in different ways. What another microcontroller can do with interrupts can most likely be achieved by a Propeller Chip. That it "does not have interrupts" is really just a terminology and implementation issue.
What the Propeller Chip offers instead of traditional interrupts is far more flexible and equally as effective. "Not having interrupts" sounds like a major failing and problem, but in reality it is not.
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